1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device such as a NAND EEPROM, and particularly to a nonvolatile semiconductor memory device employed as a binary or multiple-valued flash memory executing high-speed writing and a writing method thereof.
2. Description of the Related Art
As one kind of EEPROM, a NAND EEPROM allowing a high integration degree is known.
For formation of the NAND EEPROM, NAND cell units are formed by connecting plural memory cells in series to each other in such a way that the source and drain are shared by adjacent memory cells, and these NAND cell units are connected to bit lines with each NAND cell unit defined as one unit.
Typically the memory cell has an FETMOS structure in which a floating gate (charge accumulation layer) and a control gate are stacked over one another. A memory cell array is formed through integration in a p-type well formed in a p-type substrate or n-type substrate.
The drain side of a NAND cell unit is connected to a bit line via a selection gate, and the source side thereof is connected to a common source line via a selection gate.
The control gates of memory cells are continuously arranged along the row direction so as to serve as a word line.
This NAND-cell-unit EEPROM operates in the following manner.
Data writing is sequentially carried out from the memory cell most remote to the bit line. A high voltage Vpp (=about 20 V) is applied to the control gate of a selected memory cell, and thereby an intermediate voltage Vm (=about 10 V) is applied to the control gate of the memory cell and the selection gate on the bit line side. Furthermore, depending on data, 0 V or a voltage VCC that cuts off the selection gate (=about 3 V) is applied to the bit line.
When 0 V is applied to the bit line, this potential is transferred to the drain of the selected memory cell so that electron injection into the charge accumulation layer arises. This shifts the threshold value of the selected memory cell in the positive direction. This state is defined as “0”.
When the voltage VCC is given to the bit line, the electron injection does not arise effectively, and hence, the threshold value does not change but remains at a negative value.
This state is equivalent to the erased state and defined as “1”. The data writing is simultaneously carried out for memory cells sharing a control gate in parallel.
Data erasing is simultaneously carried out for all the memory cells in a NAND cell unit. Specifically, all the control gates are supplied with 0 V, and the p-type well is supplied with 20 V. At this time, the selection gates, bit line, and source line are also supplied with 20 V.
Thus, in all the memory cells, electrons in the charge accumulation layer are discharged to the p-type well so that the threshold value shifts in the negative direction.
For data reading, the control gate of the selected memory cell is supplied with 0 V, while the control gates of the other memory cells and the selection gates are given a supply voltage Vread (e.g., 5 V). In this state, whether or not a current that flows through the selected memory cell is detected the data reading is carried out.
Because of the limitation on the read operation, the threshold value obtained after the writing of “0” needs to be set to a value between 0 V and the voltage Vread. Therefore, write verify is carried out to detect memory cells to which “0” is insufficiently written, and rewriting data is set so that rewriting can be carried out only for the memory cells to which “0” is insufficiently written (bit-by-bit verify).
The memory cell to which “0” is insufficiently written is detected through reading (verify reading) in which the selected control gate is supplied with e.g. 0.5 V (verify voltage). Specifically, unless the threshold value of the memory cell is equal to or larger than 0.5 V, which is employed in consideration of a margin with respect to 0 V, a current flows through the selected memory cell so that insufficiency of writing of “0” thereto is detected.
Data writing is carried out through repetition of the write operation and write verify, and thereby, the write time is optimized for each memory cell so that the threshold value obtained after writing of “0” is adjusted to a value between 0 V and the voltage Vread.
In such a NAND-cell-unit EEPROM, if the write voltage Vpp at the time of writing is kept constant, the change of the threshold value of a memory cell is fast in the early phase of the writing, in which the amount of electrons in the charge accumulation layer is comparatively small, while the change of the threshold value of the memory cell is slow in the late phase of the writing, in which electrons have been injected to some extent and hence the amount of electrons in the charge accumulation layer is comparatively large. Furthermore, an electric field applied to an insulating film through which a tunnel current flows is strong in the writing early phase, while the electric field becomes weaker in the writing late phase.
Therefore, if the write voltage Vpp is set higher in order to enhance the write speed, the maximum threshold value obtained after the writing becomes higher and the threshold value distribution obtained after the writing becomes wider. In addition, the electric field applied to an insulating film through which a tunnel current flows becomes stronger, which deteriorates the reliability.
In contrast, if the voltage Vpp is set lower in order to narrow the threshold value distribution obtained after the writing, the write speed becomes lower.
In order to address the above-described problems, there is proposed and typically employed a writing scheme in which adjustment for each memory cell having different write speed characteristics is achieved through a stepwise increase in a write voltage Vpp by ΔVpp after every increment in the number of times of write verify (refer to Japanese Patent Laid-Open No. 2005-11521).